Digital transmission system with frequency weighted noise reduction

ABSTRACT

An analog-to-digital encoder uses an N dimensional quantizer to simultaneously generate N digits of the output code for an input analog signal. When the quantizer is used as a Delta modulator, the inputs to it are developed in N summing circuits. The first summing circuit has the present sample of the analog signal as an input and the other summing circuits have one of (N-1) future samples applied to their inputs, respectively. A local decoder at the output of the quantizer generates a reconstruction or approximation of the analog signal and applies it to each of the summing circuits. In addition, past error terms are stored, multiplied by weighting coefficients, and combined into signals which are also applied to the summing circuits. The proper selection of weighting coefficients and decision threshold levels in the quantizer produces an output code which has a minimum frequency weighted quantizing error.

Rosenbaum ted States Patent 11 1 DIGITAL TRANSMISSION SYSTEM WITHFREQUENCY WEIGHTED NOISE 3,500,331 3/1910 Conway 340/347x REDUCTIONPrimary Examiner-Charles D. Miller Att ne --W. L. Keefauver [75]inventor: Arnold Stephen Rosenbaum, or y Mrddletown, NJ. 7 ABSTRACT [73]Assignee: Bell Telephone Laboratories, An analog-to-digital encoder usesan N dimensional Incorporated, Murray Hill, NJ. quantizer tosimultaneously generate N digits of the output code for an input analogsignal. When the quan- [22] 1971 tizer is used as a Delta modulator, theinputs to it are [21] Appl. No.: 214,051 developed in N summingcircuits. The first summing circuit has the present sample of the analogsignal as an input and the other summing circuits have one of (5IIIIIIII 340/347 ;52:333; (N-l) future samples applied to their inputs,respec- [58] Fie'm T 325/38 tively. A local decoder at the output of thequantizer "5 333/18 generates a reconstruction or approximation of theanalog signal and applies it to each of the summing circuits. Inaddition, past error terms are stored, multi- [56] References Citedplied by weighting coefficients, and combined into sig- UNITED STATESPATENTS nals which are also applied to the summing circuits. 3,414,81912/1968 Lucky 333/18 X The proper selection of weighting coefficientsand de- 3,026,375 3/1962 Graham 325/38 X cision threshold levels in thequantizer produces an output code which has a minimum frequency weighted3:354:267 11/1967 Crater .1: "1325/38 )1 quamzmg 3,479,458 11/1969 Lordat a]. 325/42 15 Claims, 8 Drawing Figures IOO INPUT -5AMPLER COMBlNER Iv 1- T 50 A COMBINER LOCAL L DECODER ,140 F when I COMBINER I PAIENIH]JUL 1 0 I975 SHEET 3 OF 5 u r F FREQUENCY IN KC FIG. .38

FREQUENCY IN KC l I 0 I5 FREQUENCY lN KC FIG. 30

I PATENTEU JUN '3 SHEET 5 BF 5 FIG. 5

LOCAL DECODER 500 T N-l N SOURCE SAMPLES DIGITAL TRANSMISSION SYSTEMWITH FREQUENCY WEIGHTED NOISE REDUCTION BACKGROUND OF THE INVENTION Thisinvention relates to pulse code modulation (PCM) systems and, moreparticularly, to systems for encoding groups of samples of an inputsignal in such a way as to reduce the frequency weighted quantizingnoise.

In PCM encoders in general, an input analog signal is sampled at orabove the Nyquist rate. These samples are then applied to a quantizerwhich typically has the input signal range divided into an arbitrarynumber of quantizing intervals. The output generated by the quantizer isthe digital representation of the quantizing level that most closelyapproximates the sample. In other types of quantizers the digital signalgenerated depends not on the absolute value of the input signal but onthe difference between the present sample and some predicted value.Since in either case there is rarely a quantizing level or predictedvalue which is exactly the same as the input analog signal, there willbe a difference between the input analog signal and the signal reconstructed from its digital representation. This difference is called thequantizing noise.

In digital transmission systems, information about past and futuresamples of the input signal can be used to code the present sample insuch a way as to reduce the quantizing noise. In particular, futuresamples give the coder information about any change of direction-in theinput signal which is about to occur. Also, past samples show thedirection in which the signal was going previously. In prior artencoders, quantizing errors are calculated by subtracting the output ofa local decoder from the input signal. These quantizing errors are thenstored and used to vary the quantizing levels in the quantizer or to aidin predicting what the next sample will be. If these quantizing errorsare properly weighted they can be used in a way which will cause areduction in the quantizing noise in a particular frequency band withthe sacrifice of increased noise in other parts of the frequency specrum. Also, in other prior art coders future samples (samples subsequentto the one being encoded) are used to improve the quantizers ability topredict future samples in such a way as to reduce the means squarednoisewhich is the total noise in the entire frequency spectrum. From atheoretical point of view, it would seem that a more effective method ofreducing quantizing noise in a particular frequency band rather than themean squared noise over the entire spectrum could be achieved by usingboth past and future samples of the input signal. In addition, whenfuture samples are available through the use of storage and delay, it ispossible to encode the present sample and several subsequent samplessimultaneously, that is, the input samples can be encoded in groups orblocks. Therefore, by using past and future samples of an input analogsignal it is possible to perform block encoding of the input signal withreduced quantizing noise in a particular frequency range. This is trueregardless of the type of coder used.

It is therefore an object of this invention to provide a practicalsystem for block encoding an input signal in such a way as to reduce thefrequency weighted quantizing noise.

SUMMARY OF THE INVENTION The present invention is directed to reductionof the frequency weighted quantizing noise in a digital transmissionsystem by selecting the output code; according to the past, present andfuture samples of the input signal along with the possible decoderreconstructions; that minimizes this noise. This has the advantage ofgreater efficiency since all the available information about the signaland the possible coding choices is used to reduce the noise in the bandof interest without regard to the remaining frequency spectrum. Thisinvention also provides for the simultaneous generation of groups ofoutput bits.

In an illustrative embodiment of the invention, a Delta modulator isarranged to make use of the present and one future sample and three pasterrors. In this Delta modulator an input analog signal is applied to asampling circuit which samples it at several times the Nyquist rate. Theoutput of the sampling circuit is passed through a first delay linewhich delays the signal for one sampling period. If the output of thisfirst delay line is defined as the present sample, then the output ofthe sampling circuit will represent a sample which is one sampling timein the future. The present sample and the future sample are then appliedto first and second summing means, respectively. These summing meansalgebraically combine all the signals applied to their inputs andperform the same function as the summing circuit in a conventional Deltamodulator. The outputs of the first and second summing means are appliedto the two inputs of a two-dimensional quantizer, respectively. Thisquantizer simultaneously generates two output digits in joint responseto the inputs from the two summing means. The decision boundaries in thequantizer are particularly chosen so that a code is generated whichminimizes the frequency weighted quantizing noise when used inconjunction with a feedback signal, to be described later. The twooutputs of the quantizer are then sequentially applied to a localdecoder whose output will be an analog equivalent of the digitalrepresentation of the input signal. As in a conventional Deltamodulator, this signal is applied to the first and second summing meansin order to generate a difference signal for the quantizer. However, theoutput of the integrator is also subtracted from the present sample in athird summing means. This will generate a signal equivalent to thepresent quantizing error. This quantizing error is applied to the inputsof a second, third and fourth delay lines. The second delay line delaysthis present error signal for one sampling period; the third delay linedelays the error signal for two sampling periods; and the fourth delayline delays the error signal for three sampling periods. The output ofthe second delay line is passed through a first multiplier, whicheffectively multiplies it by a factor b(l). The output of the thirddelay line passes through a second multiplier, which multiplies it by afactor b(2). Likewise, the output of the fourth delay line passesthrough a third multiplier, which multiplies it by a factor b(3). Theoutputs of these multipliers are summed and applied to a combiningcircuit. In addition, the outputs of the second, third and fourth delaylines are also passed through fourth, fifth and sixth multipliers,respectively. The fourth, fifth and sixth multipliers multiply theoutputs of the delay lines by factors b(Z), b(3) and b(4), respectively.The outputs of the fourth, fifth and sixth multipliers are also summedand applied to the combining circuit.

In summary, this combination of delay lines and multipliers generatesinformation about the past error terms in the encoder. These past errorterms are then multiplied by the b coefficients which tend to weighttheir effect. These b coefficients are determined by the Fouriercoefficients of the noise penalty function desired. The combiningcircuit generates first and second feedback signals which are applied tothe first and second summing means, respectively. These feedback signalsare used to alter the difference signal from the first and secondsumming means. This corrected output of -the summing means, inconjunction with the specially selected coding boundaries in thetwo-dimensional quantizer, in effect generates coding combinations,depending on the past, present and future samples and selects the onewhich gives the minimum quantizing noise in the band of interest.

The foregoing and other features of the present invention will be morereadily apparent from the following detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic of anillustrative embodiment of the invention;

FIG. 2 is a graph of the boundaries in the quantizer of FIG. 1;

FIG. 3A is a graph of a typical frequency spectrum of the quantizingnoise of a standard Delta modulator with a sine wave input;

- FIG. 3B is the graph of a typical noise penalty function;

FIG. 3C is a graph of the b coefficients corresponding to the penaltyfunction of FIG. 38;

FIG. 3D is a graph of a typical frequency spectrum of the quantizingnoise using the encoder of FIG. 1',

FIG. 4 is an alternative arrangement for the circuit of FIG. 1; and

FIG. 5 is a schematic of an illustrative embodiment of the invention forlarge block sizes.

DETAILED DESCRIPTION Most of the quantizers developed in the past seekto reduce the total means square quantizing noise. However, in asituation where the sampling rate is far above the Nyquist rate, a greatdeal of this noise occurs in a frequency range far above the informationband and will eventually be removed by output circuit filters.

Therefore, any technique employed in a digital transmission system whichuses the available coding combinations to reduce the overall noise willbe relatively inefficient. Instead, these coding combinations should beused to reduce the noise only in the frequency band where theinformation is contained, since the other noise will be eliminated bythe system filters. While the prior art has disclosed methods forreducing some of the in-band noise using past error terms, the presentinvention utilizes both past and future samples of the input signal togreatly reduce the in-band noise. This is accomplished by minimizing ateach block encoding an estimate of the weighted noise power, D Thisestimate is derived from M past errors in conjunction with the N future.errors produced by the next block-N encoding, where block-N refers tothe simultaneous encoding of Nsamples of the input signal, one being thepresent sample and the rest being future samples. Now

if the digital representation for a sample of the input signal can takeon one of K possible values, then there are k distinct possiblesequences of past and future errors, since the past errors have alreadybeen generated and are not changed by the encoding of the futuresamples. In a Delta modulator K would be equal to 2 and in a two-bitDPCM it would be 4.

In order to arrive at the minimum weighted noise power, D the systemmust in effect compute all the kK error patterns, and then generate thedigital sequence that results in the error pattern, which gives rise tothe least amount of noise in the frequency range of interest.

However, it can be shown that it is not necessary to compute D for eachof the K possible codes every time a group of input samples is to beencoded. Instead, the concept of an L-dimensional encoding or sourcesample space can be used, where L is the sum of the number of past inputterms, M, and the number of future input terms, N. However, since thepast errors will be fixed at any particular time, the space can bereduced to N dimensions, with the present and each of the future sampleinput terms as coordinates. The effect of the past samples is thenincluded by a translation of the various coordinates. In the case of ablock-2 encoder, the space would be a simple plane as shown in FIG. 2,with the present sample measured along one axis and the future samplemeasured along the other. The factors lil and 1b, in FIG. 2 representthe translation of the coordinates in response to the past errors. Whenthe encoding problem is viewed in this geometric way, the minimizationof D is achieved by partitioning this new N-dimensional space into Kregions, each being identified with an optimum choice of the codingsequence. For the block-2 encoder these regions are indicated by theareas I, II, III, and IV in FIG. 2. Also, since the noise is to bereduced only in a particular frequency band, the effect of the variousinputs will have to be taken together. This, in part, explains theunusual shape of the boundaries in FIG. 2. Encoding, therefore, reducesto translating the coordinates in the N- dimensional space in responseto the past error terms;

- partitioning the space into regions in response to the shape andfrequency band of the noise reduction desired; and deciding in which ofthe K regions a particular set of input samples lies. FIG. 1 is apractical example of the use of this encoding technique.

FIG. 1 is an illustrative embodiment of the invention created bymodifying a Delta modulator to use a present and one future sampletogether with three past errors. In FIG. 1, the input analog signal isapplied to sampling circuit 100. This circuit samples the input signalunder the control of the local timing clock 160. The output samples, S,of this circuit are applied to a delay circuit 105. This circuit delaysthe output of the sampler by one sampling time. Therefore, if the outputof the delay circuit, S is considered to be the present sample, then theoutput of the sampler, S is a future sample, one sampling time in thefuture. The sample, S is applied to one of the positive inputs ofcombiner circuit and the sample, 8,, is applied to one of the positiveinputs of combiner circuit 110. These combiner circuits perform the samefunction as the difference circuits in a conventional Delta modulator.Therefore, the previously reconstructed signal, 5- from the localdecoder is applied to the MINUS inputs of both combiner circuits. Inaddition, feedback signals,

09 o and 41 from bias computer 140, are applied to positive inputs ofcombiners 115 and 110, respectively. The outputs of these combiners,which represent the difference between the previously reconstructedsignal and the present and future samples (plus the feedback signals),are applied to the two inputs of 2-dimensional quantizer 120. Thisquantizer simultaneously generates two digits of the output code, C andC which are loaded into shift register 125. The quantizer generatesthese codes under the control of flip-flop 165. Since flip-flop 165 iscontrolled by the local. clock 160, the quantizer will generate outputsat one-half the sampling rate. The shift register 125 is also under thecontrol of the local clock, thus producing a serial output rate that isthe same as the sampling rate. The output of the quantizer representingthe code for the present sample is stored in the next-to-last stage ofthe shift register and the output code representing the future sample isstored in the last stage. The contents of the next-to-last stage of theshift register are applied to local decoder 130. ln effect, localdecoder 130 converts the output digital code stored in the shiftregister into an analog signal which is a reconstruction of that code, SThis reconstruction signal is applied to the negative inputs ofcombiners 110 and 115 as described above. However, it is also subtractedfrom the present sample, S in summing circuit 135. This causes thegeneration of the present quantizing error term, q,,. This error term isapplied to delay circuits 141, 142 and 143 of bias computer 140, whichdelay it for one, two and three timing periods, respectively. Theoutputs of these delay circuits are applied to multiplier circuits 144,145 and 146, respectively. These circuits, in effect, multiply theoutputs of the delay circuits by the coefficients b(l), b(2) and [1(3),respectively. The outputs of multiplier circuits 144, 145 and 146 aresummed in summing circuits 150 and 151 and are applied to input 156 ofcombiner circuit 155. In addition, the outputs of delay circuits 141,142 and 143 are applied to multipliers 147, 148 and 149, respectively.Similar to the other multiplier circuits, these have the effect ofmultiplying the outputs of delay circuits 141, 142 and 143 by thecoefficients b(2), b(3) and b(4), respectively. The outputs of thesemultipliers are added together in summing circuits 152 and 153 and areapplied to input 157 of combiner circuit 155. This combiner circuitgenerates the two feedback signals 111 and 1111, which are applied tocombiners 110 and 115, respectively.

With this arrangement, a present and future sampl are generated andapplied to combiner circuits 110 and 115. In these circuits the analogreconstruction signal from the local decoder is subtracted from theinput signals in order to generate difference signals for the quantizer120. In addition, feedback signals U1, and 41 are added to thesedifference signals. If the b coefficients are given proper values and ifthe quantiz ing regions in circuits 120 are appropriately chosen, theresulting output code, C, will have minimum quantizing noise for aparticular frequency band.

The quantizing regions for quantizer 120 are shown in FIG. 2. Adetermination of the boundaries for the coding regions is made byconsidering the N- dimensional space mentioned previously. Each of the Kpossible output codes is associated with an optimum combination of inputsamples that results in the least amount of weighted quantizing noise.These o timum combinations of source samples are represented by K pointsin the encoding space. A given point in this encoding space, representedby an actual set of inputs, will then be in a particular region if it iscloser to the optimum point of that region than to any other optimumpoint. In FIG. 2 these optimum points are denoted by A, B, C and D.Therefore, the boundaries of the various regions are determined by theloci of points which are equidistant from given pairs of optimum points.However, because of the frequency weighting applied to the noise,distance in this space is not measured in the usual way, but is in factdependent on the orientation of the two points involved. Thisanisotropic nature of the space is indicatd by the fact that theequidistance lines around each optimum point in FIG. 2 have anelliptical rather than a circular shape.

If S, is defined as an M-vector of the past inputs and S, is defined asan N-vector of the future inputs, then where the positive subscriptsindicate sample periods in the future and the negative ones indicatesample periods in the past. Also, '5, and S, can similarly be defined asthe local decoder reconstructions of the digital output of thequantizer. Therefore, the past and future error vectors are,respectively,

Qu iand 61 3- Now the complete vector for the inputs is and thereconstruction vector is The distance between S and 5 in the presentanistropic space, given in matrix notation, is

where T indicates a transpose matrix and B is a transformation matrixwhich describes the anisotropic na ture of the space. Using Equations(2), (3), and (4) in Equation (5) yields which is in partitioned form.Carrying out the indicated operation, completing the square of theresult and dropping terms in O only, gives the expression where i17=B-"B Q Now, the modified distance Equation (7) can be used to find theloci of points equidistant from adjacent reconstruction points 3'; and3]; that is, (PST?) (PS3?) will indicate the equation for the boundary.Equations (2) and (7) then yield E.S.) BNST+ (El-swap All that remainsin order to completely define the quantizer of FIG. 1 is to determinethe matrix B which specifies the anisotropic nature of the space thatwill result in reduced quantizing noise according to the given noisefrequency weighting criterion. All of the error terms, both pastandfuture, represent a finite length record which can be represented by theL dimensional vector 6, where L M N. The components of this vector canthen be indexed as iq q To determine the matrix B, the weighted noisepower, D must be estimated. This can be accomplished by relying on theWeiner-Khintchine theory which states that the autocorrelation functionand the power spectral density are Fourier transforms of each other. Aderivation of this theorem can be found on pages 431 and 432 ofInformation Transmission, Modulation, and Noise by Schwartz,McGraw-Hill, 1959. However, since the vector 6 is not a function, but isonly a series of numbers, the power spectrum may be estimated by thetechnique disclosed on pages 120 to 124 of The Measurement of PowerSpectra by Blackman and Tukey, Dover Publications, 1958. Using thistechnique, one first determines the apparent autocorrelation of thefinite record {q,... q,,} as

A 1 mm) im where the largest lag time for which data is available is (LU1. The triangular shaped lag window W): an)

is then applied to the autocorrelation. A triangular shape is chosen toimplement this concept because it simplifies the mathematics. UponFourier series expansion of the windowed autocorrelation values, themodified spectral density estimate is produced. This can be expressed inmatrix form as s, (w) l/L (i x6 2) where the elements of the X matrixareX cos (i-j) tor.

(13) Now the weighted noise power estimate, D,,.,,, can be determined byintegrating the product of the spectral density and the noise penaltyfunction W(a)).

sired by comparing Equation (6) with Equation (14). Now for any blocklength encoder, the encoding region boundaries will be determined byEquation (8 and the numerical valuesfor the elements of B by Equation(15). These results can now be used with FIG. 1 to determine theencoding region in quantizer 120, the b coefficients in bias computerand the outputs of combiner 155.

In the circuit of FIG. 1, M 3 and N 2. Therefore,

the B matrix will be b 0 1) 1) 1) (2 1) (a 1) (4) B b l) b b b m 1)2) 1) (1) 1) 0) 1) 1) 1) 2) 1) (a) 1) 2) 1) 1) 1) o) 1) 1) '1) 4) 1)a) 1) 2 1) 1 1) (0 (Hi) The values of the elements of this matrix aredetermined from Equation (15), depending on the noise penalty functionW(w). A typical noise penalty function is shown in FIG. 3B. In this casea reduction of the noise only in the information band (0 to 5 ke) isdesired, and so a rectangular function is chosen. However, this functioncould be any arbitrary non-negative function and does not have to berestricted to a particular frequency range. In fact, it could be used topenalize the noise throughout the entire frequency spectrum. FIG. 3Cshows the Fourier coefficients of the function of FIG. 3B which areessentially the elements of the B matrix.

The waveform shown in FIG. 3A is a representation of the quantizingnoise spectrum of a conventional Delta modulator with a sine wave input.When the function of FIG. 3B is used in a Delta modulator constructedunder the principles of the present invention, its quantizing noisespectrum can be represented by a curve somewhat like that in FIG. 3D. Acomparison of FIGS. 3A and 3D shows that the in-band noise has beendecreased at the expense of the out-of-ba'nd noise by using the presentinvention. However, this out-of-band noise can be removed by the systemfilters.

From Equations (6) and (16) M 4 4' RON BN=B ]and where N represents theblock length.

If the reconstruction by the local decoder of the previous sample is S.and the step size is 8, the decoding rule for the delta modulator is Tofind the boundary between pattern 0,1 and 1,1 assign 5, to 0,1 and S, to1,1. Then which is the equation for the boundary. The other boundariescan be determined by using the same procedure on the other possiblecombination of outputs. An exemplified in Equation (20), the bcoefficients always appear normalized with respect to b(0). This isbecause only the shape of W(w) is important, not its absolute amplitudescale. Since b(0) is the total area under the W(m) function as shown byEquation (15), it may conveniently be scaled such that b(0) 1. In theexpressions which follow, this normalization has already been done.

10 The combining of the weighted summations of past errors is performedin the combiner 155 of bias computer 140. From Equation (7) it can beseen that the outputs of the combiner are required to be respectively thand 111, which are the components of the vector.

.Carrying out the indicated multiplication gives The signal at input 156of the combiner 155 is and the signal at input 157 is M jz h-HlqrTherefore, the combiner 155 forms the signals i11 and 111, from theseinputs according to Equations (22) and (23).

At this point the operation of the bias computer 140 which generates thefeedback terms 11: and 1,0, for combiners and has been described. Also,the boundaries of the decision regions in the quantizer have beendescribed. However, a method of implementing the quantizer remains to bedescribed. In a block-1 coder the conventional threshold detectorcircuit can be used since it is one-dimensional. However, in a block-2coder the apparatus described in U.S. Pat. No. 2,721,900 of B. M.Oliver, which issued on Oct. 25, 1955, would be useful. In using theOliver apparatus the outputs of combiners 110 and 115 would be appliedto the horizontal and vertical plates of a cathode ray tube. The face ofthe c.r.t. would then be covered with four groups of photo diodes, eachgroup covering the area representing a particular output code. Theparticular output code generated would then depend on how the combineroutput signals deflected the c.r.t. beam. When the block length isincreased beyond two, the quantizer must take on a new form in order toascertain in which region the combination of inputs lies. FIG. 4 is anillustrative embodiment of a reorganized quantizer which can be expandedto handle the greater number of inputs in larger block length encoders.

FIG. 4 is similar to FIG. 1 except that the delay lines have beenreplaced with analog shift registers and the quantizer has been dividedinto two circuits 410 and 420, which also include the combiners 110,115, and 155 of FIG. 1. The input samples are applied to analog shiftregister 400. This shift register is under the control of the outputsignal, T, of the local clock. The analog signals are stored in theshift register and translated in response to the timing pulses. Thecontents of the shift register are applied to the first bit quantizer410 along with the partial feedback signals 2,, and 2, from summingcircuits 441 and 442, respectively. In addition, the output of the localdecoder 425 is applied to the first bit quantizer. This two-dimensionalquantizer merely decides whether the first bit of the code for the twosamples should be a 1 or a 0. This is done by determining on which sideof the boundary between the 1 regions (land ll of FIG. 2) and the 0regions (III and IV) the input combination lies. This boundary isindicated by the line drawn inside quantizer 410. The output of thisquantizer is fed through switch 415 to the input of local decoder 425and to the circuit output. This switch 415 is also under the control ofthe local clock. Once this first bit has been determined, the contentsof shift register 400 are shifted one stage, whereby a new input sample,5,, is loaded into the first stage, and the signal, 8,, (now in the laststage of shift register 400) is applied to the input of the second bitquantizer 420 along with partial feedback signal 2 and the new output oflocal decoder 425. This one-dimensional quantizer generates the secondbit of the code, after switch 415 has changed position so that theoutput of quantizer 420 can be applied to the input of the local decoderand to the circuit output. This quantizer makes a simple thresholddecision based in part on the output of the first bit quantizer throughthe signal 2 After the second bit is determined switch 415 returns tothe output of quantizer 410, which generates the first bit of the codefor the block of samples 8, and S, which by then will be stored in shiftregister 400. With this arrangement, the output code is generatedsequentially and each of the quantizers determines only one of the twobits of the output code block.

As in FIG. 1, the present sample is subtracted from the output of thelocal decoder in a summing circuit, 430, in order to generate the errorterms, q. These terms are applied to analog shift register 435, which isunder the control of the local clock. At each timing pulse the errorterms are shifted right one space. Therefore, the contents of the shiftregister represent the past error terms. The outputs of various stagesof shift register 435 are multiplied by the b coefficients and aresummed in combiner circuit 440. The output of this circuit is delayedone sampling time by delay circuit 443 before it is summed with theproduct of the present error term and theb( l) coefficient. This summingoperation takes place in summing circuit 441, whose output is thepartial feedback signal This signal can be used in the formation of thesignals th and 111, in the quantizer. However, as will be shown later,it may not be necessary to form the signals i11 and #1,. With anappropriate arrangement of the quantizer it ispossible to use thepartial feedback signals 2, 2,, and ,2, directly. When a 0 prefixsubscript is used with one of these signals it indicates that it is usedin the determination of the first bit of the block of the code and a 1indicates use in the determination of the sec- 0nd bit in the block. Thepost-subscripts differentiate between the various partial feedbacksignals used to determine a code bit. The output of the combiner 440 isalso summed with the contents of the last stage of shift register 435multiplied by the coefficient b(M+l) in summing circuit 442, whoseoutput is partial feedback term This arrangement allows for thesimultaneous generation of feedback terms 2,, and 2, with the use of onemultistage shift register. The product of b(M+l) and the contents of thelast stage of shift register 435 are delayed one sampling period bydelay circuit 444. The output of delay circuit 444 is then summed insumming circuit 445 with the output of summing circuit 441, 2 to formthe partial feedback signal,

which is used in the determination of the second bit in quantizer 420.It should be noted that a good approximation to the signal 2 can beachieved without the output of delay circuit 444, since the b(M+l)coefficient will usually be very small.

The sequentially operating block encoder of FIG. 4 can be implementedusing the arrangement in the Oliver patent with two groups ofphotodiodes forquantizer 410, and a simple threshold detecting circuitfor quantizer 420. However, as the block length increases, a differentarrangement for the quantizer must be used. This new arrangement willallow this circuit to be expanded to become a block-N encoder, as shownin FIG. 5. The initial step in such an expanded encoder is to make onlythe first digit decision in a block-N encoding, using M past errors asbefore. This decision is then used to update the analog reconstruction5:, to S thereby determining an additional error term, Now the M+lerrors can be used to make a first digit decision in the remaining block(N-l) encoding. This establishes 5,, q, and gives M+2 error terms. Thiscontinues until the last encoding, which is just a block-l decisionusing M+N-l errors. This bit-by-bit encoding process, when implementedas described, produces the desired output code without explicit timebuffering of the input source samples or the output code bits.

in FIG. 5 the analog shift register 500 is the same as the shiftregister 400 of FIG. 4 except that additional stages have been added tohandle the increased number of future input samples. Also, the quantizerhas been divided into N separate units. The first digit encoder, 512, isan N dimensional quantizer with inputs from each of the N stages of theanalog shift register 500. It generates the first bit of the output codefor the block of input samples contained in shift register 500. Thesecond digit encoder, 520, is an (N-l) dimensional quantizer with inputsfrom all except the first stage of the shift register. Howver, since itmakes its decision during the second timing interval, after the contentsof the shift register has moved, it considers the (N-l block of inputsfrom S to S Each of the succeeding digit encoders has one less inputthan the preceding encoder and makes its decision based on a block ofinputs reduced by dropping the earlier input terms. The last digitencoder is a one-dimensional quantizer with an input from only the laststage of the shift register. At

the time it makes its decision, this last stage will contain the inputterm S As in FIG. 4, each of the quantizers or digit encoders haspartial feedback terms 2 supplied to it, so that the updated effect ofpast quantizing errors is thereby included in the sequential blockdecision making process.

The outputs of the various quantizing units are collected by commutatingswitch 515, which applies them to both the circuit output and the inputof local decoder 525. This local decoder generates an analog equivalentof the digital code appearing at the output. Difference circuit 530 isused to subtract this analog equivalent signal from the input samples.As with the other circuit arrangements, this creates quantizing errorterms which are used in bias computer 540 to generate the partialfeedback signals for the various units of the quantizer.

Each of the N separate digit encoders in FIG. is arranged differentlythan the quantizers in the other embodiments of the invention. The FirstDigit Encoder has N inputs and circuitry which will differentiatebetween 2 different coding regions; but generates only the first bit ofthe code. These regions are divided into two classes, those which have a0" for the first bit and those which have a 1. The quantizer thendetermines in which of the two classes the combination of input signalsbelongs. This is done by making all possible comparisons of the relativedistance of the source sample combination to pairs of code points whereone point is in the 0 class and the other is in the 1 class. The resultsof these comparisons are logically combined to determine in which classthe closest code point lies. Each comparison of code points can beimplemented with a different threshold detecting circuit through the useof Equation (8). In this case the code points will be in oppositeclasses. Various summing, difference and multi lier circuits are used todetermine if Is7 B-;+ Y a (st-WEN 3 7 where 3: is the reconstruction ofthe code point in the 0 class, Ii; is the reconstruction of the codepoint in the 1 class, 3", is the input combination, and Z= (3Q, is thevector of partial feedback terms,

2 (j) at (25) The threshold circuit determines if the sense of theinequality in Equation (24) is correct or not. If it is, this shows thatthe input combination is closer to code point than to point 37, and thevalue of an internal digital bit is set to 1121f it is not, the inputcombination is closer to point 25 and the internal bit is set to 0. Thenthe internal digital bits from the comparisons using the other pairs ofcode points from opposite classes are combined in logic circuits togenerate the digit encoder output bit.

By way of example, the code points of FIG. 2 are divided into the 0"class containing codes 0,0 and 0,1, and the 1" class containing 1,] and1,0. Then four separate circuits are arranged according to Equation (24)to determine if the input is closer to code points A or B than it is tocode points C or D. These four circuits will generate internal digitalbits, depending on the comparison, according to the followingconditions:

Output of (26) C0= Ckt. *1 (Ckt. *3)(Ckt. *4).

It should be noted that with this arrangement it is not necessary togenerate the complete feedback terms th and 41 used in FIG. 1. Instead,only the partial feedback terms 2 need be generated. This results in asavings in design effort since it is not necessary to obtain the inverseof a large B matrix in order to get IF= 8f 86;. Additional savings canalso be obtained by not comparing all the possible pairs of code points.Some comparisons have very little effect on the result. In someinstances, certain comparisons may rigorously be eliminated since theyinvolve redundant terms in the logical expression for the output. Forexample, the comparison between points A and D represented by Ckt. *2was not necessary for the result in Equation (27).

In this way the quantizer can be expanded to handle any number of futureinputs with the only practical limitation being the complexity of thecircuitry required for this determination.

Although preferred embodiments of this invention have been shown anddescribed, it will be understood by those skilled in the art thatvarious modifications may be made without departing from the spirit andscope of this invention.

I claim: I

1. In a digital transmission system an encoder for converting an inputanalog signal into an output digital code, comprising:

means for obtaining a present and (N-l) future samples of said inputanalog signal at a particular sampling rate, where N is an integer;

means for generating an analog equivalent signal from the output digitalcode, the analog equivalent signal being an analog replica of the outputdigital code;

means for generating quantizing error terms based upon the differencebetween the analog equivalent signal of the digital code and the presentsample of the input analog signal;

means for storing M successive previously generated quantizing errorterms; and

means for quantizing the present and (N-l) future samples of the inputanalog signal into the digital code according to a plurality ofquantizing regions, which produce a reduced frequency weightedquantizing error, said means for quantizing including means for varyingthe quantizing regions to correct for quantizing errors as indicated bythe M successive previously generated quantizing error terms, and meansfor encoding the quantized signals. 2. A digital encoder for convertingan input analog signal into a digital code comprising:

I means for obtaining a present and (N-l future samples of said inputanalog signal'at a particular sampling rate; a plurality of summingmeans for combining each sample with a separate feedback signal;

quantizing means responsive to the outputs of said plurality of summingmeans for simultaneously generating the combination of bits ofthe'digital code, representing the present and (N-l) future samples ofthe input analog signal;

means for generating an analog equivalent signal from the bits of thedigital code;

means for generating quantizing error terms by computing the differencebetween the analog equivalent signal of the digital code and the presentsample of the input analog signal;

means responsive to the present and previously generated quantizingerror terms for generating the separate feedback signals, the feedbacksignals being generated in such a way asto allow the quantizing means togenerate the digital code which produces a reduced frequency weightedquantizing error'according to a noise penalty function when takentogether with thevpresent and previously generated quantizing errorterms.

3. An encoder as claimed 'in claim 2 wherein said means for obtaining apresent and ('N--1) future samples of said input analog signalcomprises:

means for sampling the-amplitude of the input signal and holding thesample fora period'of time; and

means for storing the shifting at the sampling rate a plurality ofsuccessive samples of the input signal,

th'e earliest stored sample being considered the present sample and allsubsequent samples being considered future samples.

4. An encoder as claimed in claim 2 wherein said quantizing meanscomprises means for determining in which of a plurality of encodingregions the combination of outputs from said summing means belongs andgenerating digital bits for the output code whichrepresent that region.

5. An encoder as claimed in claim 4 wherein the boundary betweenencoding regions is determined by the equation g L) 4" A (EL- "BNJ H(FIJI) B Q2= i) "ms, 37), with-i: being the analog reconstruction of thedigital'bits representing one region, S: being the analog reconstructionof the digital bits representing another "region, B and ,B beingsegments of a matrix B Hail BTEBM B being an (M N) dimensional matrixwhose ele-' ments are W(w) being the noise penalty function whichdescribes the frequency weighting desired, 1' being the period of thesampling rate, i indicating the row of the B matrix, j indicating thecolumn of the B matrix, 0: being the radian frequency, 8,, being thematrix of the first N rows and columns of B, B being the matrix of thelast M rows and columns of B, B being the matrix of the first u 7 H il BQ;- 8. An encoder as claimed in claim 7 wherein said means for storingand shifting comprises an'an'alogshift register;

9;An encoder as claimed in claim 7 whereinsaid means for storing andshifting comprises a plurality of means for delaying the present errorterms'for aplurality of successive sampling periods.

10. An encoder as claimed in claim' 2 wherein said encoder is arrangedto function as a delta modulator by further including means forsubtracting the output of said means for generating an analog equivalentsignal from the present and future samples of the input signal. 11. Anencoder'as claimed in claim 10 wherein said means for generating ananalog equivalent signal comprises:

a digital shift register having a plurality of stages, the

output bits of the quantizing means being uniformly loaded in parallelinto the stages of said shift digital register, the first bit of thecode being loaded into the last stage of said digital shift register andthe last bit of the code being loaded into the first stage of saiddigital shift register; and

means for integrating impulses generated in response to the bits storedin said digital shift register as they are shifted into the last stageof said digital shift register.

12. A digital encoder for converting an input analog signal into adigital code comprising:

means for obtaining a present and (N-l successive future samples of saidinput analog signal;

N quantizing means for sequentially generating the output code, thefirst quantizing means generating the first bit of the code in responseto a first partial feedback signal, the presentsample, and the (N-lfuture samples, the succeeding quantizing means each generating asucceeding bit of the code in response to succeeding separate partialfeedback signals and one less sample than the preceding quantizingmeans, the one less sample being the one least in the future, the N' ofsaid quantizing means generating the last bit of the code in response toa nals being those analog equivalent signals of digital codes having a 1as the first bit, said zero analog equivalent signals being those analogequivalent signals of digital codes having a as the first bit;

last partial feedback signal and the most future sample;

means for sequentially collecting the output bits of said N quantizingmeans and generating an analog equivalent signal in response to thebits;

means for generating quantizing error terms by computing the differencebetween the analog equivalent signal of the digital code during the timea bit is generated and the sample of the input analog signal used in thegeneration of that bit which is the one least in the future; and

means responsive to the present and previously genand means forlogically combining the internal bits of said plurality of comparisonmeans to determine if the combination of inputs to a particularquantizing means is closer to a particular one analog equivalent signalthan to any zero analog equivalent signal and generating a 1" output bitfor said particular quantizing means if it is and a 0' output bit if itis not. 14. A digital encoder as claimed in claim 13 wherein saidcomparison means comprises circuit means for determining if the inputcombination is closer to the one Hated quantizing error terms forgenerating the analo e uivalent si nals than to the zero anal euivseparate partial feedback signals, the partial feedq 0g q alentsignals according to the expression:

back signals being generated in such a way as to T A T allow each of theN quantizing means to generate 2Q 3;+ 6;- ?l) 2 SL3?) a di ital bit ofthe out ut di ital code which ro- J ducfs a reduced freql lency weightedquanti ing 3; being one of the one analog equwalem 811 hsl erroraccording to a noise penalty function when being i h analog eqlfivaleniSignals lh l in error terms. i D r 13. i digital encoder as claimed inclaim 12 wherein ticular quamlzlhg means, N being s egmem of each ofsaid N quantizing means comprises: Weighting matrix B determmed y the Py a plurality f comparison means f comparing ll function, T indicatingthe transpose of the indicated possible pairs f one a d zero a al i l tmatrix, and a positive result for the expression indicay signals for aparticular quantizer with the combinag that the input combination is 7than t0 tion of inputs to said particular quantizer and gen- 15. Adigital encoder as claimed in claim 14 wherein crating an internal 1 bitif the input combination said partial feedback terms are given by thematrix is closer to the one analog equivalent signal than to BC, thezero analog equivalent signal, and an internal 0 bit if it is not, saidone analog equivalent sig-

1. In a digital transmission system an encoder for converting an inputanalog signal into an output digital code, comprising: means forobtaining a present and (N-1) future samples of said input analog signalat a particular sampling rate, where N is an integer; means forgenerating an analog equivalent signal from the output digital code, theanalog equivalent signal being an analog replica of the output digitalcode; means for generating quantizing error terms based upon thedifference between the analog equivalent signal of the digital code andthe present sample of the input analog signal; means for storing Msuccessive previously generated quantizing error terms; and means forquantizing the present and (N-1) future samples of the input analogsignal into the digital code according to a plurality of quantizingregions, which produce a reduced frequency weighted quantizing error,said means for quantizing including means for varying the quantizingregions to correct for quantizing errors as indicated by the Msuccessive previously generated quantizing error terms, and means forencoding the quantized signals.
 2. A digital encoDer for converting aninput analog signal into a digital code comprising: means for obtaininga present and (N-1) future samples of said input analog signal at aparticular sampling rate; a plurality of summing means for combiningeach sample with a separate feedback signal; quantizing means responsiveto the outputs of said plurality of summing means for simultaneouslygenerating the combination of bits of the digital code, representing thepresent and (N-1) future samples of the input analog signal; means forgenerating an analog equivalent signal from the bits of the digitalcode; means for generating quantizing error terms by computing thedifference between the analog equivalent signal of the digital code andthe present sample of the input analog signal; means responsive to thepresent and previously generated quantizing error terms for generatingthe separate feedback signals, the feedback signals being generated insuch a way as to allow the quantizing means to generate the digital codewhich produces a reduced frequency weighted quantizing error accordingto a noise penalty function when taken together with the present andpreviously generated quantizing error terms.
 3. An encoder as claimed inclaim 2 wherein said means for obtaining a present and (N-1) futuresamples of said input analog signal comprises: means for sampling theamplitude of the input signal and holding the sample for a period oftime; and means for storing the shifting at the sampling rate aplurality of successive samples of the input signal, the earliest storedsample being considered the present sample and all subsequent samplesbeing considered future samples.
 4. An encoder as claimed in claim 2wherein said quantizing means comprises means for determining in whichof a plurality of encoding regions the combination of outputs from saidsumming means belongs and generating digital bits for the output codewhich represent that region.
 5. An encoder as claimed in claim 4 whereinthe boundary between encoding regions is determined by the equation(Se - Si)T BN Sf + (Se - Si)T Beta Qp 1/2 (Se - Si)T BN(Se + Si), withSe being the analog reconstruction of the digital bits representing oneregion, Si being the analog reconstruction of the digital bitsrepresenting another region, BN and Beta being segments of a matrix Bdescribing the frequency weighting, Qp being the vector of pastquantizing error terms, and T indicating the transpose of the indicatedmatrix.
 6. An encoder as claimed in claim 5, wherein the matrix B inpartition form is given by
 7. An encoder as claimed in claim 6 whereinsaid means for generating the separate feedback signals comprises: meansfor storing and shifting at the sampling rate a plurality of quantizingerror terms; means for multiplying the stored quantizing error terms bycoefficients of the B matrix and generating partial products by summingthe results; and means for combining the partial products to produce thefeedback terms psi such that psi BN 1 Beta Qp.
 8. An encoder as claimedin claim 7 wherein said means for storing and shifting comprises ananalog shift register.
 9. An encoder as claimed in claim 7 wherein saidmeans for storing and shifting comprises a plurality of means fordelaying the present error terms for a plurality of successive samplingperiods.
 10. An encoder as claimed in claim 2 wherein said encoder isarranged to function as a delta modulator by further including means forsubtracting the output of said means for generating an analog equivalentsignal from the present and future samples of the input signal.
 11. Anencoder as claimed in claim 10 wherein said means for generating ananalog equivalent signal comprises: a digital shift register having aplurality of stages, the output bits of the quantizing means beinguniformly loaded in parallel into the stages of said shift digitalregister, the first bit of the code being loaded into the last stage ofsaid digital shift register and the last bit of the code being loadedinto the first stage of said digital shift register; and means forintegrating impulses generated in response to the bits stored in saiddigital shift register as they are shifted into the last stage of saiddigital shift register.
 12. A digital encoder for converting an inputanalog signal into a digital code comprising: means for obtaining apresent and (N-1) successive future samples of said input analog signal;N quantizing means for sequentially generating the output code, thefirst quantizing means generating the first bit of the code in responseto a first partial feedback signal, the present sample, and the (N-1)future samples, the succeeding quantizing means each generating asucceeding bit of the code in response to succeeding separate partialfeedback signals and one less sample than the preceding quantizingmeans, the one less sample being the one least in the future, the Nth ofsaid quantizing means generating the last bit of the code in response toa last partial feedback signal and the most future sample; means forsequentially collecting the output bits of said N quantizing means andgenerating an analog equivalent signal in response to the bits; meansfor generating quantizing error terms by computing the differencebetween the analog equivalent signal of the digital code during the timea bit is generated and the sample of the input analog signal used in thegeneration of that bit which is the one least in the future; and meansresponsive to the present and previously generated quantizing errorterms for generating the separate partial feedback signals, the partialfeedback signals being generated in such a way as to allow each of the Nquantizing means to generate a digital bit of the output digital codewhich produces a reduced frequency weighted quantizing error accordingto a noise penalty function when taken together with previouslygenerated quantizing error terms.
 13. A digital encoder as claimed inclaim 12 wherein each of said N quantizing means comprises: a pluralityof comparison means for comparing all possible pairs of one and zeroanalog equivalent signals for a particular quantizer with thecombination of inputs to said particular quantizer and generating aninternal ''''1'''' bit if the input combination is closer to the oneanalog equivalent signal than to the zero analog equivalent signal, andan internal ''''0'''' bit if it is not, said one analog equivalentsignals being those analog equivalent signals of digital codes having a''''1'''' as the first bit, said zero analog equivalent signals beingthose analog equivalent signals of digital codes having a ''''0'''' asthe first bit; and means for logically combining the internal bits ofsaid plurality of comparison means to determine if the combination ofinputs to a particular quantizing meAns is closer to a particular oneanalog equivalent signal than to any zero analog equivalent signal andgenerating a ''''1'''' output bit for said particular quantizing meansif it is and a ''''0'''' output bit if it is not.
 14. A digital encoderas claimed in claim 13 wherein said comparison means comprises circuitmeans for determining if the input combination is closer to the oneanalog equivalent signals than to the zero analog equivalent signalsaccording to the expression: (Sl - Si)TBN Sf + (Sl - Si)T Sigma - 1/2(S - Si)TBN (Sl + Si) > 0, Si being one of the one analog equivalentsignals, Sl being one of the zero analog equivalent signals, Sf beingthe combination of inputs to said particular quantizing means, Sigmabeing the partial feedback term for said particular quantizing means, BNbeing a segment of weighting matrix B determined by the noise penaltyfunction, T indicating the transpose of the indicated matrix, and apositive result for the expression indicating that the input combinationis closer to Sl than to Si.
 15. A digital encoder as claimed in claim 14wherein said partial feedback terms are given by the matrix Sigma BetaQp.